LVDS
MS90C386
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24bit Flat Panel Display (FPD)LVDS signal receiver at +3.3V 145MHz
Datasheet Download
Overview
MS90C386B/MS90C386P/MS90C386 chips to 4 channel of low voltage differential signal (an LVDS) converted to 28 bit TTL data. The clock channel is input in parallel with the data channel. At a clock frequency of 145MHz, 24bit RGB data, 3bit LCD timing data and 1bit control data are transmitted in each LVDS data channel at a rate of 1015Mbps. When the input clock frequency is 145MHz, the data transmission rate is 507.5Mbytes/sec. This chip, combined with MS90C385B, is ideal for solving electromagnetic interference and cable length problems at the high bandwidth and high-speed TTL signal level.
Key Features
- • Frequency range: 20-145MHz clock signal
- • Fewer buses reduce wire size and expense
- • Power supply 3.3V
- • Low power mode
- • Supports VGA, SVGA, XGA, SXGA
- • 4.06Gbps data throughput
- • 507.5Megabytes/sec bandwidth
- • Reduce LVDS swing to reduce electromagnetic interference (300mV LVDS swing)
- • No external structure is required for the PLL
- • Follow the TIA/EIA-644 LVDS standard
- • TSSOP56 package
Key Features
Surveillance camera
Desktop/laptop
Printer
